The present invention relates to an image display apparatus which is capable of producing an image display with lower electric power consumption.
FIGS. 27 and 28 illustrate two known image display apparatus. FIG. 27 shows an example of the configuration of a known TFT liquid crystal display panel. The pixels 210, each having liquid crystal capacitance 209, are arranged in a matrix configuration in the display portion of the panel (only a single pixel 210 is illustrated in FIG. 27 for simplifying the drawing). The pixel 210 is connected through the gate line 211 and the AC drive signal line 207 to the gate line drive circuit 215, and it is connected through the positive signal line 212 and the negative signal line 213 to the signal line drive circuit 214. The pixel 210 has a SRAM (Static Random Access Memory) composed of the inverter 203 and the inverter 204, and its two data input and output nodes are connected through the data input switches 201 and 202 to the positive signal line 212 and the negative signal line 213, respectively. Those data nodes are also connected to the liquid crystal capacitance write switches 205 and 206. The liquid crystal capacitance is connected through the liquid crystal capacitance write switches 205 and 206 to the AC drive signal line 207 and the reset voltage line 208.
Now, the operation in this pixel arrangement will be described. As the gate line drive circuit 215 opens and closes the data input switches 201 and 202 for the designated pixel line through the gate line 211, the 1-bit complementary image data on the positive signal line 212 and the negative signal line 213 supplied by the signal drive circuit 214 are put into the SRAM composed of the inverter 203 and the inverter 204 in the pixel 210. As long as the electric power is applied, the SRAM statically holds the 1-bit image data as supplied in the above manner. One of the liquid crystal capacitance write switches 205 and 206 is turned on by the image data written in the SRAM, so that, the voltage selected exclusively from either of the AC drive signal line 207 or the reset voltage line 208 is applied to the liquid crystal capacitance 209. Thus, if the AC drive signal line 207 is selected, AC voltage is applied to the liquid crystal capacitance 209, and if the reset voltage line 208 is selected, no voltage is applied to the liquid crystal capacitance 209. Owing to this operation, this liquid crystal display panel can continue to display the 1-bit display image even if the scan of the gate line 211 by the gate line drive circuit 215 and the data output to the positive signal line 212 and to the negative signal line 213 by the signal line drive circuit 214 are suspended.
The known display panel construction as described above is described in detail in Japanese Patent Application Laid-open No. 8-286170 (1996).
Next, referring to FIG. 28, another known pixel arrangement will be described. FIG. 28 shows an example of the configuration of the TFT liquid crystal display panel using a prior art. The pixels 230, each having liquid crystal capacitance, are arranged in a matrix configuration between the pixel electrodes 224 and the opposed electrodes 225 in the display portion of the panel (only a single pixel 230 is illustrated in FIG. 28 for simplifying the drawing). The pixel 230 is connected through the gate line 231 to the gate line drive circuit 235, and it is connected through the signal line 232 to the signal line drive circuit 234. The pixel 230 has a DRAM (Dynamic Random Access Memory) composed of the data input switch 221 and the hold capacitance 222, and the terminal of its data input switch 221 is connected to the signal line 232. The data node of the DRAM is connected to the gate of the pixel drive switch 223, and the liquid crystal capacitance is connected through the pixel drive switch 223 to the common electrode line 233. The common electrode line 233 is connected to the common electrode drive circuit 237, and the opposed electrode 225 is connected to the opposed electrode drive circuit 236.
Now the operation in this pixel arrangement will be described. As the gate line drive circuit 235 opens and closes the data input switch 221 for the designated pixel line through the gate line 231, the l-bit image data on the signal line 232 supplied by the signal line drive circuit 234 is put into the DRAM composed of the data input switch 221 and the hold capacitance 222. In response to the image data written into the DRAM, the pixel drive switch 223 is locked so as to hold an on state or an off state. As AC voltage is applied to the opposed electrode by the opposed electrode drive circuit 236 and a designated voltage is applied to the common electrode line 233 by the common electrode drive circuit 237, if the pixel drive switch 223 is turned on, AC voltage is applied to the liquid crystal capacitance between the pixel electrode 224 and the opposed electrode 225; and, in contrast, if the pixel drive switch 223 is turned off, no voltage is applied to the liquid crystal capacitance. Owing to this operation, the liquid crystal display panel can continue to display the 1-bit display image until the data in the DRAM is lost due to leakage current, even if the scan of the gate line 231 by the gate line drive circuit 235 and the data output onto the signal line 232 by the signal line drive circuit 234 are suspended. In order to hold the display image data statically, it is only required to rewrite the DRAM periodically by scanning the gate line 231 with the gate line drive circuit 235 and putting out the data onto the signal line with the signal line drive circuit 234.
The known display panel construction as described above is described in detail in Japanese Patent Application Laid-Open Number 9-258168 (1997).
According to the display panels described above, it will be appreciated that the scan of the gate line and the data output onto the signal line may be suspended or the number of those operations can be reduced, which leads to the reduction in the electric power consumption for TFT liquid crystal display panels. However, with these known display panels, it is difficult to achieve simultaneously the reduction in the electric power consumption and a reduction in the cost.
In the display panel in which an SRAM is installed inside the pixel, there is an advantageous aspect in that the operations for scanning the gate line and for data output to the signal line can be completely suspended and the electric power consumption can be reduced; however, but in contrast, there is a disadvantageous aspect in that the pixel structure becomes inevitably sophisticated as the number of transistors formed in the SRAM is larger. As the throughput of manufactured devices inevitably will be reduced for the sophisticated pixel structure, the price of the image display apparatus may increase.
In the display panel in which a DRAM is installed inside the pixel, there is an advantageous aspect in that the pixel structure can be simplified as the number of transistors formed in the DRAM is reduced and a reduction in the price of the image display apparatus may be expected due to an increase in the throughput of the manufactured devices. However, since the DRAM requires rewrite (refresh) operations, the operations for scanning the gate line by the gate line drive circuit 235 and for data output onto the signal line by the signal line drive circuit 234 can not completely suspended. As for the data output onto the signal line, since it is required to supply the data onto the signal line having a relatively larger parasitic capacitance as many times as the number of pixels for writing the overall display, there still remains a problem in that a further reduction in the electric power consumption can not achieved easily. In addition, since it is required to reserve the display image data to be used for the rewrite operation at any other part, additional electric power consumption and cost may be inevitable.
And furthermore, though the known display panels described above assume that 1-bit display image data will be used for an individual pixel, it is expected that the handling of multi-bit display image data will be necessary, as well as achieving a reduction in the electric power consumption and a reduction in the cost of the manufactured device.